Structured testing of the combinational logic systems, used to implement VLSI circuits, requires the use of test patterns (vectors) consisting of a predetermined set of input stimuli for the combinational logic block under test. Typically, these test patterns are generated using some form of computer automated test pattern generation (ATPG) software. Accordingly, the optimum structured test methodology is one designed to facilitate its use with the ATPG software. One such structured test method uses scan path flip-flops to implement a shift path for loading a test vector, and applying the test vector of a logic block under test. In a conventional scan path design, during test mode scan operation, the flip-flops' parallel outputs are constantly changing in a way that reflects the scan data (test vector) being shifted through the scan path. Typically, the flip-flop's system logic parallel output and its scan output are the same output. In cases where the flip-flop's parallel outputs drive normal combinational logic, the fact that the parallel outputs are the same as the scan output does not present a problem. If however, the logic being driven by this essentially random data generates signals that activate asynchronous sets or resets of scan path flip-flops, some facility is required to prevent the spurious corruption of scan data. This phenomenon is frequently referred to as the "bare bit" problem.
The capabilities and limitations of Automatic Test Pattern Generation (ATPG) software impose additional constraints on the design of scan path flip-flops. For example, in state of the art structured design, there is a design rule that prohibits the use of asynchronous resets, except for initialization (i.e. as necessary for system power-up), and this exception applied only if the initilization is activated from a primary input. Resets for purposes other than initilization are thus generally limited to affecting the flip-flops synchronously. The primary purpose of this design rule is to address the bare bit problem.
Some prior art solutions have employed special test control signals to seize control of the scan flip-flop's asynchronous set and reset signals during the test mode, and thus, resolve the bare bit problem. Typically, these prior art solutions involve seizing control of the reset signal in the test mode with a boundary-scan cell that serves no additional function in the system. Such boundary-scan cells require a special control signal that it not used for any other purpose. Thus, the generation of the special test control signal requires additional test system overhead, and therefore, in some test environments these prior art solutions are not feasible.